1. Field of the Invention
The present invention relates to an output buffer circuit, in which the offset voltage of a data driver is detected by an offset compensating circuit composed of a small number of switching elements and resistors and is fed back to an input stage so that an output voltage becomes equal to an input voltage. Therefore, the data driver can be reduced in size, the offset voltage can be accurately compensated, and data can be transmitted at a high rate because a time for compensating the offset voltage is not required.
2. Description of the Related Art
Although the resolution of a SOM (Spatial Optical Modulator) driver IC currently stays at 8 bits, a 10-bit resolution or more will be practically used within several years.
However, in order to generate a 10-bit gradation voltage, such a data driver is needed that can output a gradation voltage of which the offset voltage (the different between input and output voltages) is in the range of less than ±1 mV, considering that the output voltage is in the range of about 4 V. Accordingly, it can be found that a data driver with a considerably high precision is needed, considering that the offset voltage of a current 8-bit data driver is in the range of ±3 mV to ±10 mV. However, if the current 8-bit data driver is used, an image signal cannot be accurately transmitted due to the influence of an offset voltage as the output resolution increases.
Therefore, in order to reduce the offset voltage of a data driver, the application of various offset compensating circuits to the data driver is attempted. For example, there are provided an auto zeroing method, a chopper stabilization method, and a ping-pong method. The auto zeroing method is most frequently used.
FIG. 1A is a diagram showing an output buffer 100 which is modeled according to the related art, and FIGS. 1B and 1C are diagrams showing an offset voltage generated in the related art.
The offset voltage, which is generated in the output node A of an output stage in accordance with time after an input voltage signal is applied to an input stage of the output buffer 100 of FIG. 1A, can be divided into a positive offset voltage (FIG. 1B) and a negative offset voltage (FIG. 1C). The positive offset voltage is generated because an output voltage is larger than an input voltage, and the negative offset voltage is generated because an input voltage is larger than an output voltage. Such an offset voltage prevents an image signal from being accurately transmitted during a data transmission time t. The offset voltage is generated by various causes. As the main cause, the mismatch between transistors which occurs in a process of manufacturing semiconductor circuits can be exemplified. That is, the positive or negative offset voltage is generated when signal-path transistors, which process a main signal and sub signal of a semiconductor circuit input stage, are manufactured to have a different size in the process of manufacturing semiconductor circuits.
FIG. 2 is a circuit diagram showing a conventional output buffer 200, to which an offset compensating circuit using the auto zeroing method is applied.
As shown in FIG. 2, the conventional output buffer circuit 200 is composed of an input stage (201a to 201f) of which one end receives an input voltage and the other end receives an output voltage, a floating current source (202a to 202d) which biases a class AB output stage (204a and 204b), a summing circuit (203a to 203h) which is connected to the input stage (201a to 201f), the floating current source (202a to 202d), and the class AB output stage (204a and 204b) so as to sum up the current supplied from the input stage (201a to 201f) and the internal current supplied from the floating current source (202a to 202d), the class AB output stage (204a and 204b) which, when the difference between the input and output voltages is larger than 0, increases a current flowing in the output stage so as to output a voltage, and an offset compensating circuit which is connected to the input stage (201a to 201f) and the class AB output stage (204a and 204b) and is composed of switches and a capacitor so as to compensate the offset voltage.
The offset compensating circuit is composed of a capacitor Coff which stores an offset voltage and switches SW1 to SW4 which, when an offset voltage is generated, are complementarily turned on so as to compensate the offset voltage.
The operation in which an offset voltage is compensated by the offset compensating circuit is divided in two steps. Referring to the buffer circuit 200 shown in FIG. 2, the operation in which the offset voltage is compensated will be described.
Here, the offset voltage of the output buffer circuit 200 itself is referred to as Voff and an input voltage is referred to as Vin. In the first step, the first and second switches SW1 and SW2 are turned on and the third and fourth switches SW3 and SW4 are turned off, so that the offset voltage Voff of the output buffer circuit 200 is stored in the capacitor Coff. That is, since the first and second switches SW1 and SW2 are turned on, the voltage of the minus (−) node of the capacitor Coff becomes Vin and the voltage of the plus (+) node of the capacitor Coff becomes Vin+Voff. Accordingly, a voltage which is applied to both ends of the capacitor becomes Voff.
The offset voltage Voff stored in the capacitor Coff is compensated in the second step when the third and fourth switches SW3 and SW4 are turned on and the first and second switches SW1 and SW2 are turned off. That is, if the third and fourth switches SW3 and SW4 are turned on, the voltage at the plus (+) node of the capacitor is converted into Vin, and the voltage at the minus (−) node of the capacitor becomes Vin−Voff in accordance with the principle of conservation of charge. Accordingly, a voltage which is applied to the input stage (201a to 201f) of the output buffer circuit 200 becomes Vin−Voff. Since the offset voltage of the output buffer circuit 200 itself is defined as Voff, the offset voltage Voff is compensated so that the output voltage becomes equal to the input voltage Vin.
In the conventional output buffer circuit as described above, however, a time for sampling offset, that is, a time for blocking the signal path of input and output voltages in the first step and for compensating the offset voltage in the second step is required. Therefore, a time required for transmitting data cannot be secured sufficiently, thereby preventing high-rate data transmission.
Further, as the offset voltage is compensated by using a switch, an offset voltage which is different from the actual offset voltage is generated due to the charge injection effect occurring at the time of switching. Then, the perfect compensation of the offset voltage is not carried out.
Furthermore, the offset voltage can be stored in not only the capacitor composing the offset compensating circuit but also a generated parasitic capacitor. Therefore, in order to prevent the resultant error, a capacitor with more than a constant capacitance value is required, so that the size of the output buffer circuit increases.